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Resource optimised reconfigurable modular parallel pipelined stochastic approximation-based self-tuning regulator architecture with reduced latency

机译：资源优化的可重构模块化并行流水线随机近似自调整调节器架构，具有减少的延迟

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Varghese Mathew Vaidyan; Ashok Shankar;
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年度 2015
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1. Resource optimised reconfigurable modular parallel pipelined stochastic approximation-based self-tuning regulator architecture with reduced latency [J] . Varghese Mathew Vaidyan, Ashok Shankar The Journal of Engineering . 2015,第9期

机译：资源优化的可重构模块化并行流水线基于随机逼近的自调整调节器架构，减少了延迟
2. A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator [J] . T. ANANTHAN, M. V. VAIDYAN ACM transactions on reconfigurable technology and systems . 2013,第4期

机译：自整定调节器的可重配置并行硬件实现
3. A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization [J] . Xiangyu Zhang, Fengwei An, Lei Chen, IEEE transactions on circuits and systems . I , Regular papers . 2018,第10期

机译：用于学习矢量量化的模块化和可重构管道架构
4. Parallel implementation of finite state machines for reducing the latency of stochastic computing [C] . Cong Ma, David J. Lilja International Symposium on Quality Electronic Design . 2018

机译：并行执行有限状态机以减少随机计算的延迟
5. Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture [D] . Rahman, Kamela Choudhury. 2016

机译：基于大规模并行和流水线忆阻状态IMPLY逻辑的可重构体系结构的完整设计方法论
6. An optimised pipeline for parallel image-based quantification of gene expression and genotyping after in situ hybridisation [O] . Tomasz Dobrzycki, Monika Krecsmarik, Florian Bonkhofer, 2018

机译：原位杂交后基于平行图像的基因表达和基因分型定量分析的优化管线
7. Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture [O] . Yongjoo Kim, Jongeun Lee, Jinyong Lee, 2014

机译：利用sImD可重构架构开发流水线和数据并行
8. State-Space Self-Tuning Regulators for General Multivariable Stochastic Systems. [R] . Shieh, L. S., Bao, Y. L., Chang, F. R. 1989

机译：一般多变量随机系统的状态空间自校正调节器。

Resource optimised reconfigurable modular parallel pipelined stochastic approximation-based self-tuning regulator architecture with reduced latency

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